1. Field of the Invention
The present invention relates to a method for achieving line-to-line synchronization. The invention allows for extremely accurate horizontal synchronizing signal (Hsync) Synchronization while not interfering with clock generation. The method overcomes line-to-line synchronization problems in a simplified design, while providing near-zero line-to-line placement error.
2. Description of the Prior Art
A critical parameter which affects the output quality of any raster scanning device is the accuracy of the line-to-line synchronization. Raster scanning devices such as laser printers or video displays typically supply a horizontal synchronization signal (HSYNC) as the laser, or illuminating beam, crosses the plane of a fixed detection means, usually located before, and near the beginning of each new scan. The HSYNC signal generated on each new scan serves as an indication that the beam is crossing a fixed horizontal reference point. Digital systems such as laser printers, must monitor the HSYNC signal and use it as a reference for the serialization of digital video data for the scan. Since digital systems are clocked at fixed intervals with no synchronous relationship to the physical generation of the HSYNC signal, line-to-line horizontal synchronization error can result.
For example, a digital system with a memory bitmap in which a single bit corresponds to a physical 1/600".times.1/600" area of the printed page might be clocked at a period equal to the time required for the laser to sweep 1/600" across the imaging surface. Therefore, the leftmost serialized bit of any scan is placed at a fixed number of clocks after the clock which first sampled an active HSYNC. Since the HSYNC signal can occur at any position between the clock edges, but the digital logic can produce new bits of video data coincident with the clock edges, the physical placement of the first pel, (a pel being one bit of a memory bitmap used to represent an image in a digital memory system,) may be in error by as much as 1/600". Any inaccuracies in line-to-line synchronization cause misalignment of pels which result in visible artifacts.
The bit is translated by the imaging device into a physical space corresponding to the image resolution, such as 1/600".times.1/600". The time required by the imaging device to sweep across that area is referred to as the pel time. PELCLK is a clock used to operate portions of a digital imaging system whose period is one pel time.
A slice is generally the number of discrete periods into which each pel is subdivided. By operating on a portion of a pel, various duty-cycles and print improvements may be obtained. The slice time corresponds to the pel time divided by the number of slices which make up the pel. SLICECLK is a clock used to operate portions of a digital imaging system whose period is one slice time.
There are three primary methods of reducing line-to-line placement error.
The first involves a high speed slice clock. A design can address line-to-line synchronization by running an internal clock, SLICECLK, at a higher frequency than the clock that is synchronous with the pel generation (PELCLK). The PELCLK signal is usually generated via divider logic which produces a new active edge of PELCLK every n counts of a counter. Using such an approach, it is possible to sample the HSYNC signal at a higher frequency than PELCLK. After sampling an HSYNC signal with the SLICECLK logic, the logic must restart PELCLK for each scan by resetting the divider logic which generates PELCLK. The foregoing method produces a first edge of PELCLK which has a maximum error equal to the period of SLICECLK. For example, if the SLICECLK runs at 4 times the frequency of PELCLK, the placement error can be as much as 1/4 pel, or 1/2400" in a 600 dpi (dot per inch) printer.
While the foregoing method provides more line-to-line synchronization accuracy than simply using PELCLK, PELCLK must either be stopped at the end of a scan and restarted on HSYNC, or it must contain some discontinuity at the point where the PELCLK divider is reset by HSYNC.
A second method utilizes high speed slice clock with PELCLK synchronization on either edge of SLICECLK. Previous Lexmark.TM. printer designs have employed a method using a high frequency clock that samples HSYNC on both rising and falling edges. When an HSYNC is sampled, control logic then generates a SLICECLK which is either the "true" or "inverted" version of the sampling clock dependent on which edge first sampled the active HSYNC signal. As a result, the first SLICECLK edge is within 1/2 of a clock period from the HSYNC signal.
As was the case in the previous method, the PELCLK is generated by logic which divides SLICECLK. The logic turns SLICECLK off at the end of a scan and restarts it when either edge of the high frequency sampling clock sees the HSYNC signal. Since the divider that generates PELCLK is also reset at the end of the scan, the first SLICECLK of a new scan restarts the divider, thus synchronizing PELCLK to within 1/2 of a SLICECLK. For example, if the SLICECLK runs at four times the frequency of PELCLK, the placement error can be as much as 1/8 pel or 1/4800" in a 600 dpi printer.
The foregoing method has the advantage of providing more line-to-line synchronization accuracy than simply using PELCLK or SLICECLK. The accuracy is potentially two times better than using a single edge of SLICECLK. However, the method has disadvantages. The SLICECLK must be stopped at the end of a scan and restarted on HSYNC, thereby producing a discontinuity in SLICECLK both at the end of the scan when attempting to stop the clock, and at the beginning of the scan when attempting to restart a new one. Such discontinuities can result in clock pulse widths that violate timing specifications for clocked components. Since the SLICECLK is high frequency, pausing and restarting the clock without generating glitches becomes more difficult.
Furthermore, as laser printer speeds continue to increase, so must the clock frequencies required to accurately sample HSYNC. At sixteen pages per minute print speed on the Optra.TM. family of printers, a clock frequency of 53 mHz is required to provide 1/4800" line-to-line synchronization accuracy. At 24 pages per minute, a frequency of approximately 85 mHz is required to provide the same accuracy. With today's available silicon geometries, it is impractical to clock an entire complex pel generation logic block at such frequencies.
A third method involves clock selection. U.S. Pat. Nos. 5,438,353, 5,109,283 and 5,122,883 describe similar methods of achieving line-to-line synchronization. These patents describe a system which produces the lower frequency PELCLK and achieves synchronization with the HSYNC signal by restarting the PELCLK with its first edge nearly coincident with HSYNC. The designs generate several clocks at the pel frequency. Each clock is successively offset in phase from its predecessor by a delay element. As the HSYNC signal becomes active, the logic examines all clocks and selects the clock which has the closest phase relationship to HSYNC. The selected clock then becomes PELCLK for the scan, and the process is repeated on successive scans. FIG. 1 illustrates such a method.
The clock selection method is advantageous by allowing near perfect accuracy in the phase relationship between HSYNC and the PELCLK. The phase difference between HSYNC and PELCLK can be as small as one delay element. Also, there is no need for high frequency logic which samples HSYNC.
The clock selection method has disadvantages. Most printer systems require the ability to subdivide a pel into slices to perform such actions as pel duty cycle modulation and pel edge shifting. This requires the use of a clock that is higher frequency than PELCLK. If each scan starts a new PELCLK with various phase relationships, it may be difficult or impossible to use higher frequency SLICECLK since it has no consistent phase relationship with PELCLK. In order to use this approach in a system which requires both a PELCLK and a SLICECLK, the design may need to select among phase-shifted SLICECLK's on each new scan and then generate PELCLK by dividing SLICECLK. With a clock selection method, it becomes more difficult to stop and restart SLICECLK due to its higher frequencies.